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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
15  
Pin Capacitance  
Pin Capacitance  
Table 11: Pin Capacitance for Cyclone V Devices  
Symbol  
Description  
Value  
Unit  
pF  
CIOTB  
CIOLR  
Input capacitance on top and bottom I/O pins  
6
6
6
Input capacitance on left and right I/O pins  
pF  
COUTFB  
Input capacitance on dual-purpose clock output and feedback pins  
pF  
Hot Socketing  
Table 12: Hot Socketing Specifications for Cyclone V Devices  
Symbol  
Description  
Maximum  
300  
Unit  
μA  
IIOPIN (DC)  
DC current per I/O pin  
IIOPIN (AC)  
AC current per I/O pin  
8(15)  
mA  
mA  
mA  
IXCVR-TX (DC)  
IXCVR-RX (DC)  
DC current per transceiver transmitter (TX) pin  
DC current per transceiver receiver (RX) pin  
100  
50  
Internal Weak Pull-Up Resistor  
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.  
(15)  
The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew  
rate.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
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