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Switching Characteristics
Memory Block Specifications
Table 27 lists the Cyclone V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in fMAX
.
Table 27. Memory Block Performance Specifications for Cyclone V Devices
Resources Used
Performance
Memory
Mode
Unit
ALUTs
Memory
–C6
–C7, –I7
–C8, –A7
Single port, all supported widths
0
1
420
350
300
MHz
MHz
Simple dual-port, all supported
widths
0
0
1
1
420
340
350
290
300
240
MLAB
Simple dual-port with read and
write at the same address
MHz
ROM, all supported width
0
0
1
1
420
315
350
275
300
240
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported
widths
0
1
315
275
240
MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
M10K
Block
0
1
275
240
180
MHz
True dual port, all supported
widths
0
0
1
1
315
315
275
275
240
240
MHz
MHz
ROM, all supported widths
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
1
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
Cyclone V Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
