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5CEBA2F23C6N 参数 Datasheet PDF下载

5CEBA2F23C6N图片预览
型号: 5CEBA2F23C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484]
分类和应用: 可编程逻辑
文件页数/大小: 64 页 / 1355 K
品牌: INTEL [ INTEL ]
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Electrical Characteristics  
Page 15  
Table 19. Differential I/O Standard Specifications for Cyclone V Devices (Part 2 of 2)  
(2)  
(2), (9)  
VCCIO (V)  
Min Typ Max Min Condition Max Min  
VCM  
VID (mV) (1)  
VICM(DC) (V)  
VOD (V)  
VOCM (V)  
I/O Standard  
Condition Max Min Typ Max Min Typ Max  
1.8  
=
HiSpi  
2.375 2.5 2.625 100  
0.05  
1.25 V  
Notes to Table 19:  
(1) The minimum VID value is applicable over the entire common mode range, VCM  
.
(2) RL range: 90 RL 110 Ω  
(3) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to 1.85 V  
for data rate below 700 Mbps.  
(4) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.  
(5) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interface in Supported Altera Device Families.  
(6) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.  
(7) For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.  
(8) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to  
1.95 V for data rate below 700 Mbps.  
(9) This applies to default pre-emphasis setting only.  
December 2013 Altera Corporation  
Cyclone V Device Datasheet