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5AGXFB3H4F35I5 参数 Datasheet PDF下载

5AGXFB3H4F35I5图片预览
型号: 5AGXFB3H4F35I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 362730-Cell, CMOS, PBGA1152, FBGA-1152]
分类和应用: 时钟可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-20  
Differential SSTL I/O Standards  
VIL(DC) (V)  
VIH(DC) (V)  
VIL(AC) (V)  
Max  
VIH(AC) (V)  
Min  
VOL (V)  
Max  
VOH (V)  
Min  
(14)  
IOL  
I/O Standard  
IOH(14) (mA)  
(mA)  
Min  
Max  
Min  
Max  
HSTL-15  
Class II  
VREF – 0.1  
VREF + 0.1  
VREF – 0.2  
VREF + 0.2  
0.4  
VCCIO – 0.4  
16  
–16  
HSTL-12  
Class I  
–0.15  
–0.15  
VREF – 0.08 VREF + 0.08 VCCIO + 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO  
VREF – 0.08 VREF + 0.08 VCCIO+ 0.15 VREF – 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO  
8
–8  
–16  
HSTL-12  
Class II  
16  
HSUL-12  
VREF – 0.13 VREF + 0.13  
VREF – 0.22 VREF + 0.22 0.1 × VCCIO 0.9 × VCCIO  
Differential SSTL I/O Standards  
Table 1-17: Differential SSTL I/O Standards for Arria V Devices  
VCCIO (V)  
Typ  
VSWING(DC) (V)  
VX(AC) (V)  
VSWING(AC) (V)  
I/O Standard  
Min  
Max  
Min  
Max  
Min  
Typ  
Max  
Min  
Max  
SSTL-2  
2.375  
2.5  
2.625  
0.3  
0.25  
0.2  
VCCIO + 0.6  
VCCIO/2 –  
0.2  
VCCIO/2 +  
0.2  
0.62  
VCCIO + 0.6  
Class I, II  
SSTL-18  
1.71  
1.425  
1.283  
1.8  
1.5  
1.89  
1.575  
1.45  
VCCIO + 0.6  
VCCIO/2 –  
0.175  
VCCIO/2 +  
0.175  
0.5  
VCCIO + 0.6  
2(VIL(AC) – VREF  
2(VIL(AC) – VREF)  
Class I, II  
(15)  
SSTL-15  
VCCIO/2 –  
0.15  
VCCIO/2 +  
0.15  
2(VIH(AC)  
)
Class I, II  
VREF)  
(15)  
SSTL-135  
1.35  
0.18  
VCCIO/2 –  
0.15  
VCCIO/2  
VCCIO/2 +  
0.15  
2(VIH(AC)  
VREF  
)
(14)  
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8  
mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the  
datasheet.  
The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC)  
and VIL(DC)).  
(15)  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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