AV-51002
2015.12.16
2-47
Transmitter High-Speed I/O Specifications
C4, I4
C3, I3L
Typ
Symbol
Conditions
Unit
Min
Max
Min
Typ
Max
(183)
(183)
Emulated Differential I/O
Standards with Three
SERDES factor J = 4 to 10 (190)
—
840
—
840
Mbps
External Output Resistor
Networks - fHSDR (data rate)
(189)
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
—
—
—
—
45
—
—
—
—
50
160
0.1
300
0.2
55
—
—
—
—
45
—
—
—
—
50
160
0.1
ps
UI
ps
UI
%
tx Jitter - True Differential I/O
Standards
Total Jitter for Data Rate
< 600 Mbps
Total Jitter for Data Rate
600 Mbps - 1.25 Gbps
325
0.25
55
t
x Jitter - Emulated Differential
I/O Standards with Three
External Output Resistor
Network
Total Jitter for Data Rate
< 600 Mbps
tDUTY
Transmitter output clock duty
cycle for both True and Emulated
Differential I/O Standards
True Differential I/O Standards
—
—
—
—
200
250
—
—
—
—
200
300
ps
ps
Emulated Differential I/O
Standards with three external
output resistor networks
tRISE & tFALL
True Differential I/O Standards
—
—
—
—
150
300
—
—
—
—
150
300
ps
ps
TCCS
Emulated Differential I/O
Standards
(189)
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
(190)
Arria V GZ Device Datasheet
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