AV-51002
2015.12.16
2-24
Transceiver Clocks
Transceiver Clocks
Table 2-23: Transceiver Clocks Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about
device ordering codes, refer to the Arria V Device Overview.
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
fixedclkclock frequency
PCIe
Receiver Detect
—
100 or
125
—
—
100 or
125
—
MHz
Reconfiguration clock (mgmt_clk_
clk) frequency
—
100
—
125
100
—
125
MHz
Related Information
Arria V Device Overview
For more information about device ordering codes.
Receiver
Table 2-24: Receiver Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about
device ordering codes, refer to the Arria V Device Overview.
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min Typ Max
Min
Typ
Max
Supported I/O Standards
Data rate (Standard PCS) (142)
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
600 9900
(143)
,
—
—
600
—
8800
Mbps
(142)
(143)
The line data rate may be limited by PCS-FPGA interface speed grade.
To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
Arria V GZ Device Datasheet
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