AV-51002
2017.02.10
2-44
Periphery Performance
Description
Min
Typ
Max
Unit
Diode ideality factor
1.006
1.008
1.010
—
Periphery Performance
I/O performance supports several system interfaces, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X
bus interface. General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are capable of a typical 167 MHz and 1.2-LVCMOS
at 100 MHz interfacing frequency with a 10 pF load.
Note: e actual achievable frequency depends on design- and system-specific factors. Ensure proper timing closure in your design and perform
HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
High-Speed Clock Specifications
Table 2-39: High-Speed Clock Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
Arria V GZ devices support the following output standards using true LVDS output buffer types on all I/O banks.
• True RSDS output standard with data rates of up to 230 Mbps
• True mini-LVDS output standard with data rates of up to 340 Mbps
Arria V GZ Device Datasheet
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