AV-51002
2017.02.10
1-8
HPS Power Supply Operating Conditions
Symbol
Description
Minimum(5)
Typical
Maximum(5)
Unit
VCCL_GXBL
VCCL_GXBR
VCCL_GXBL
VCCL_GXBR
GX and SX speed grades—clock network power
(lef side)
1.08/1.12
1.1/1.15(6)
1.14/1.18
V
GX and SX speed grades—clock network power
(right side)
GT and ST speed grades—clock network power
(lef side)
1.17
1.20
1.23
V
GT and ST speed grades—clock network power
(right side)
Related Information
Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines
Provides more information about the power supply connection for different data rates.
HPS Power Supply Operating Conditions
Table 1-5: HPS Power Supply Operating Conditions for Arria V SX and ST Devices
is table lists the steady-state voltage and current values expected from Arria V system-on-a-chip (SoC) devices with ARM®-based hard processor
system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Arria V
Devices table for the steady-state voltage values expected from the FPGA portion of the Arria V SoC devices.
Symbol
Description
Condition
–C4, –I5, –C5, –C6
–I3
Minimum(7)
Typical
Maximum(7)
Unit
HPS core
voltage and
periphery
circuitry
power
1.07
1.1
1.13
V
1.12
1.15
1.18
V
VCC_HPS
supply
(5)
(7)
e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
Arria V GX, GT, SX, and ST Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
