AV-51002
2017.02.10
2-37
Core Performance Specifications
Core Performance Specifications
Clock Tree Specifications
Table 2-33: Clock Tree Performance for Arria V GZ Devices
Performance
Symbol
Unit
C3, I3L
C4, I4
580
Global and Regional Clock
Periphery Clock
650
500
MHz
MHz
500
PLL Specifications
Table 2-34: PLL Specifications for Arria V GZ Devices
Symbol
Parameter
Min
5
Typ
Max
800
650
325
160
1600
1300
60
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
Input clock frequency (C3, I3L speed grade)
Input clock frequency (C4, I4 speed grade)
Input frequency to the PFD
—
—
—
—
—
—
—
(167)
fIN
5
fINPFD
5
fFINPFD
Fractional Input clock frequency to the PFD
PLL VCO operating range (C3, I3L speed grade)
PLL VCO operating range (C4, I4 speed grade)
50
600
600
40
(168)
fVCO
tEINDUTY
Input clock or external feedback clock input duty
cycle
(167)
(168)
is specification is limited in the Quartus II sofꢂare by the I/O maximum frequency. e maximum I/O frequency is different for each I/O
standard.
e VCO frequency reported by the Quartus II sofꢂare in the PLL Usage Summary section of the compilation report takes into consideration the
VCO post-scale counter K value. ereꢃore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
Arria V GZ Device Datasheet
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