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5AGXBA5D4F31C5N 参数 Datasheet PDF下载

5AGXBA5D4F31C5N图片预览
型号: 5AGXBA5D4F31C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 190000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 184 页 / 1761 K
品牌: INTEL [ INTEL ]
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AV-51002  
2017.02.10  
1-9  
HPS Power Supply Operating Conditions  
Symbol  
Description  
Condition  
3.3 V  
3.0 V  
2.5 V  
3.3 V  
3.0 V  
2.5 V  
1.8 V  
1.5 V  
1.35 V (9)  
1.2 V  
3.3 V  
3.0 V  
2.5 V  
1.8 V  
Minimum(7)  
3.135  
2.85  
Typical  
3.3  
Maximum(7)  
3.465  
3.15  
Unit  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HPS I/O  
pre-driver  
power  
(8)  
VCCPD_HPS  
3.0  
supply  
2.375  
3.135  
2.85  
2.5  
2.625  
3.465  
3.15  
3.3  
3.0  
2.375  
1.71  
2.5  
2.625  
1.89  
HPS I/O  
buffers  
power  
VCCIO_HPS  
1.8  
supply  
1.425  
1.283  
1.14  
1.5  
1.575  
1.418  
1.26  
1.35  
1.2  
3.135  
2.85  
3.3  
3.465  
3.15  
HPS reset  
and clock  
input pins  
power  
3.0  
VCCRSTCLK_HPS  
2.375  
1.71  
2.5  
2.625  
1.89  
supply  
1.8  
VCCPLL_HPS  
HPS PLL  
analog  
2.375  
2.5  
2.625  
voltage  
regulator  
power  
supply  
(7)  
e power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.  
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.  
(8)  
(9)  
VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when  
VCCIO_HPS is 3.3 V.  
VCCIO_HPS 1.35 V is supported for HPS row I/O bank only.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation