Page 20
Switching Characteristics
Table 21. Transceiver Specifications for Arria V GT and ST Devices (Part 1 of 3)
Transceiver Speed Grade 3
Symbol/
Description
Conditions
Unit
Max
Min
Typ
Reference Clock
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2)
HCSL, and LVDS
,
Supported I/O Standards
Input frequency from REFCLKinput pins
Rise time
—
27
—
710
MHz
20% to 80% of rising clock
edge
—
—
400
ps
80% to 20% of falling clock
edge
Fall time
—
45
—
—
—
400
55
ps
%
Duty cycle
—
300/2000
Peak-to-peak differential input voltage
—
200
mV
(3)
Spread-spectrum modulating clock
frequency
PCI Express (PCIe)
PCIe
30
—
—
33
—
kHz
—
0 to
–0.5%
100
Spread-spectrum downspread
On-chip termination resistors
—
—
—
—
—
—
Ω
VICM (AC coupled)
1.2
V
HCSL I/O standard for the
VICM (DC coupled)
250
—
550
mV
PCIe reference clock
10 Hz
100 Hz
1 KHz
—
—
—
—
—
—
—
—
—
—
—
—
-50
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmitter REFCLK Phase Noise (1)
-110
-120
-120
-130
10 KHz
100 KHz
≥1 MHz
2000
1%
RREF
—
—
—
Ω
Transceiver Clocks
fixedclkclock frequency
Transceiver Reconfiguration Controller IP
PCIe Receiver Detect
—
—
75
125
—
—
MHz
MHz
125
(mgmt_clk_clk) clock frequency
Receiver
Supported I/O Standards
Data rate (6-Gbps Transceiver) (15)
Data rate (10-Gbps transceiver) (15)
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
—
—
—
—
611
0.611
—
—
—
—
—
6553.6
10.3125
1.2
Mbps
Gbps
V
(4)
Absolute VMAX for a receiver pin
Absolute VMIN for a receiver pin
–0.4
—
V
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
