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5AGXFB3K4F40I5N 参数 Datasheet PDF下载

5AGXFB3K4F40I5N图片预览
型号: 5AGXFB3K4F40I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, PBGA1517, ROHS COMPLIANT, FBGA-1517]
分类和应用: 可编程逻辑
文件页数/大小: 122 页 / 2566 K
品牌: INTEL [ INTEL ]
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Page 12  
Electrical Characteristics  
Internal Weak Pull-Up Resistor  
Table 13 lists the weak pull-up resistor values for Arria V devices.  
All I/O pins have an option to enable weak pull-up except the configuration, test, and  
JTAG pins. For more information about the pins that support internal weak pull-up  
and internal weak pull-down features, refer to the Arria V GT, GX, ST, and SX Device  
Family Pin Connection Guidelines.  
Table 13. Internal Weak Pull-Up Resistor Values for Arria V Devices  
Symbol  
Description  
Conditions (V) (1)  
Value (2) Unit  
VCCIO = 3.3 5%  
25  
25  
25  
25  
25  
25  
25  
25  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
kΩ  
VCCIO = 3.0 5%  
VCCIO = 2.5 5%  
Value of the I/O pin pull-up resistor before and during  
configuration, as well as user mode if you have enabled the  
programmable pull-up resistor option.  
V
CCIO = 1.8 5%  
CCIO = 1.5 5%  
RPU  
V
V
V
CCIO = 1.35 5%  
CCIO = 1.25 5%  
VCCIO = 1.2 5%  
Notes to Table 13:  
(1) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO  
(2) Valid with 10% tolerances to cover changes over PVT.  
.
I/O Standard Specifications  
Table 14 through Table 19 list the input voltage (VIH and VIL), output voltage (VOH and  
OL), and current drive characteristics (IOH and IOL) for various I/O standards  
V
supported by Arria V devices.  
For an explanation of terms used in Table 14 through Table 19, refer to “Glossary” on  
page 1–64.  
Table 14. Single-Ended I/O Standards for Arria V Devices (Part 1 of 2)  
VCCIO (V)  
VIL (V)  
VIH (V)  
VOL (V)  
VOH (V)  
(1)  
(1)  
IOL  
IOH  
I/O Standard  
(mA) (mA)  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
Max  
Min  
3.3-V LVTTL  
3.135  
3.3  
3.465 –0.3  
0.8  
1.7  
3.6  
0.45  
2.4  
4
2
–4  
–2  
3.3-V  
LVCMOS  
3.135  
2.85  
2.85  
3.3  
3
3.465 –0.3  
0.8  
0.8  
1.7  
1.7  
1.7  
3.6  
3.6  
3.6  
0.2  
0.4  
0.2  
VCCIO – 0.2  
2.4  
3.0-V LVTTL  
3.15  
3.15  
–0.3  
–0.3  
2
–2  
3.0-V  
LVCMOS  
3
0.8  
V
CCIO – 0.2  
0.1  
–0.1  
3.0-V PCI  
3.0-V PCI-X  
2.5 V  
2.85  
2.85  
3
3
3.15  
3.15  
0.3 x VCCIO  
0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO  
0.9 x VCCIO  
0.9 x VCCIO  
2
1.5  
1.5  
1
–0.5  
–0.5  
–1  
0.35 x VCCIO 0.5 x VCCIO VCCIO + 0.3 0.1 x VCCIO  
2.375  
2.5  
2.625 –0.3  
1.89 –0.3 0.35 x VCCIO  
1.575 –0.3 0.35 x VCCIO  
0.7  
1.7  
3.6  
0.4  
0.65 x  
VCCIO  
1.8 V  
1.5 V  
1.71  
1.8  
1.5  
VCCIO + 0.3  
0.45  
VCCIO – 0.45  
2
2
–2  
–2  
0.65 x  
VCCIO  
1.425  
VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO  
Arria V GX, GT, SX, and ST Device Datasheet  
December 2013 Altera Corporation