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550 参数 Datasheet PDF下载

550图片预览
型号: 550
PDF下载: 下载PDF文件 查看货源
内容描述: 奔腾4处理器,支持超线程技术 [Pentium 4 Processors Supporting Hyper-Threading Technology]
分类和应用:
文件页数/大小: 96 页 / 1585 K
品牌: INTEL [ INTEL ]
 浏览型号550的Datasheet PDF文件第54页浏览型号550的Datasheet PDF文件第55页浏览型号550的Datasheet PDF文件第56页浏览型号550的Datasheet PDF文件第57页浏览型号550的Datasheet PDF文件第59页浏览型号550的Datasheet PDF文件第60页浏览型号550的Datasheet PDF文件第61页浏览型号550的Datasheet PDF文件第62页  
Land Listing and Signal Descriptions  
Table 4-2. Numerical Land Assignment  
Table 4-2. Numerical Land Assignment  
Land  
#
Signal Buffer  
Type  
Land  
#
Signal Buffer  
Type  
Land Name  
Direction  
Land Name  
Direction  
F19  
F20  
F21  
F22  
F23  
F24  
F25  
F26  
F28  
F29  
G1  
VSS  
D41#  
Power/Other  
H2  
H3  
FC6  
VSS  
Power/Other  
Power/Other  
Common Clock  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Input  
Source Synch Input/Output  
Source Synch Input/Output  
Power/Other  
D43#  
H4  
RSP#  
TESTHI10  
VSS  
Input  
Input  
VSS  
H5  
RESERVED  
TESTHI7  
TESTHI2  
TESTHI0  
BCLK0  
RESERVED  
VSS  
H6  
Power/Other  
Power/Other  
Power/Other  
Clock  
Input  
Input  
Input  
Input  
H7  
VSS  
H8  
VSS  
H9  
VSS  
H10  
H11  
H12  
H13  
H14  
H15  
H16  
H17  
H18  
H19  
H20  
H21  
H22  
H23  
H24  
H25  
H26  
H27  
H28  
H29  
H30  
J1  
VSS  
VSS  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Source Synch  
VSS  
G2  
FC1  
Input  
Input  
VSS  
G3  
TESTHI8  
TESTHI9  
FC7  
VSS  
G4  
Input  
DP1#  
DP2#  
VSS  
Common Clock Input/Output  
Common Clock Input/Output  
Power/Other  
G5  
Output  
G6  
RESERVED  
DEFER#  
BPRI#  
G7  
Common Clock  
Common Clock  
Input  
Input  
VSS  
Power/Other  
G8  
VSS  
Power/Other  
G9  
D16#  
Source Synch Input/Output  
VSS  
Power/Other  
G10  
G11  
G12  
G13  
G14  
G15  
G16  
G17  
G18  
G19  
G20  
G21  
G22  
G23  
G24  
G25  
G26  
G27  
G28  
G29  
G30  
H1  
RESERVED  
DBI1#  
VSS  
Power/Other  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
Source Synch Input/Output  
VSS  
Power/Other  
DSTBN1#  
D27#  
VSS  
Power/Other  
VSS  
Power/Other  
D29#  
VSS  
Power/Other  
D31#  
VSS  
Power/Other  
D32#  
VSS  
Power/Other  
D36#  
VSS  
Power/Other  
D35#  
GTLREF_SEL  
BSEL1  
VTT_OUT_LEFT  
FC3  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Output  
Output  
Output  
Input  
DSTBP2#  
DSTBN2#  
D44#  
J2  
D47#  
J3  
RESERVED  
VSS  
RESET#  
TESTHI6  
TESTHI3  
TESTHI5  
TESTHI4  
BCLK1  
BSEL0  
BSEL2  
GTLREF  
Common Clock  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Output  
Input  
J4  
Power/Other  
J5  
REQ1#  
REQ4#  
VSS  
Source Synch Input/Output  
Source Synch Input/Output  
Power/Other  
J6  
J7  
J8  
VCC  
Power/Other  
J9  
VCC  
Power/Other  
Power/Other  
Power/Other  
Power/Other  
J10  
J11  
J12  
VCC  
Power/Other  
VCC  
Power/Other  
VCC  
Power/Other  
58  
Datasheet  
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