Electrical Specifications
Table 2-10. GTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit Notes
2,3
V
Input Low Voltage
Input High Voltage
Output High Voltage
0.0
GTLREF – (0.10 * V
)
CC
V
IL
3,4,5
V
GTLREF + (0.10 * V
)
V
V
V
IH
CC
CC
CC
3,5
V
0.90*V
N/A
V
OH
CC
V
/
CC
I
Output Low Current
A
OL
[0.50*RR
+R
]
ON_MIN
TT_MIN
6
I
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Buffer On Resistance
N/A
N/A
6.33
8
± 200
± 200
10.33
12
µA
LI
7
I
µA
LO
8
R
Ω
on_compatible
8
R
Ω
on_optimized
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The V referred to in these specifications is the instantaneous V
V
IL
.
CC
CC
4.
5.
V
V
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IH
and V may experience excursions above V
.
CC
IH
OH
6. Leakage to V with pin held at V
.
SS
CC
7. Leakage to V with pin held at 300 mV.
CC
8. These specifications are different depending on whether the platform is forward compatible to the Celeron D proces-
sor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous gen-
eration processor but has some level of compatibility with the Celeron D processor. An optimized platform is one
designed specifically for the Celeron D processor; however, it may have some level of compatibility with previous
generation processors.
Table 2-11. Asynchronous GTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
2,3
V
Input Low Voltage
0.0
V
/2 – (0.10 * V )
CC
V
V
IL
CC
3,4,5,6
5,6,7
8
V
Input High Voltage
V
/2 + (0.10 * V
)
V
IH
CC
CC
CC
CC
V
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Buffer On Resistance
0.90*V
—
V
V
OH
OL
CC
I
V
/[0.50*R
+R ]
ON_MIN
A
CC
TT_MIN
9
I
N/A
N/A
6.33
8
± 200
± 200
10.33
12
µA
µA
W
W
IL
10
I
LO
11
R
on_compatible
11
R
on_optimized
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals
V
IL
V
V
V
= GTLREF + (0.10 * V ) and V = GTLREF – (0.10 * V ).
IH
IH
IH
CC IL CC
4.
5.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
and V may experience excursions above V
.
CC
OH
6. The V referred to in these specifications refers to instantaneous V
.
CC
CC
7. All outputs are open drain.
8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
9. Leakage to V with pin held at V
.
SS
CC
10. Leakage to V with pin held at 300 mV.
CC
26
Datasheet
INTEL [ INTEL ]
