欢迎访问ic37.com |
会员登录 免费注册
发布采购

325119-001 参数 Datasheet PDF下载

325119-001图片预览
型号: 325119-001
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔® Xeon®处理器E7-8800 / 2800分之4800产品系列 [Intel® Xeon® Processor E7-8800/4800/2800 Product Families]
分类和应用:
文件页数/大小: 174 页 / 3951 K
品牌: INTEL [ INTEL ]
 浏览型号325119-001的Datasheet PDF文件第135页浏览型号325119-001的Datasheet PDF文件第136页浏览型号325119-001的Datasheet PDF文件第137页浏览型号325119-001的Datasheet PDF文件第138页浏览型号325119-001的Datasheet PDF文件第140页浏览型号325119-001的Datasheet PDF文件第141页浏览型号325119-001的Datasheet PDF文件第142页浏览型号325119-001的Datasheet PDF文件第143页  
Thermal Specifications  
• Assured Write FCS (AW FCS) failure. Note that under most circumstances, an  
Assured Write failure will appear as a bad FCS. However, when an originator issues  
a poorly formatted command with a miscalculated AW FCS, the client will  
intentionally abort the FCS in order to guarantee originator notification.  
6.3.4.2  
Completion Codes  
Some PECI commands respond with a completion code byte. These codes are designed  
to communicate the pass/fail status of the command and also provide more detailed  
information regarding the class of pass or fail. For all commands listed in Section 6.3.2  
that support completion codes, each command’s completion codes is listed in its  
respective section. What follows are some generalizations regarding completion codes.  
An originator that is decoding these commands can apply a simple mask to determine  
pass or fail. Bit 7 is always set on a failed command, and is cleared on a passing  
command.  
Table 6-16. Completion Code Pass/Fail Mask  
0xxx xxxxb  
1xxx xxxxb  
Command passed  
Command failed  
Table 6-17. Device Specific Completion Code (CC) Definition  
Completion  
Description  
Code  
0x00..0x3F  
0x40  
Device specific pass code  
Command Passed  
0x4X  
Command passed with a transaction ID of ‘X’ (0x40 | Transaction_ID[3:0])  
Device specific pass code  
0x50..0x7F  
CC: 0x80  
Error causing a response timeout. Either due to a rare, internal timing condition or a  
processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET  
or S1 states.  
CC: 0x81  
CC: 0x82  
CC: 0x83  
CC: 0x84  
CC: 0x85  
CC: 0x86  
CC:0xFF  
Thermal configuration data was malformed or exceeded limits.  
Thermal status mask is illegal  
Invalid counter select  
Invalid Machine Check Bank or Index  
Failure due to lack of Mailbox lock or invalid Transaction ID  
Mailbox interface is unavailable or busy  
Unknown/Invalid Mailbox Request  
Note:  
The codes explicitly defined in this table may be useful in PECI originator response  
algorithms. All reserved or undefined codes may be generated by a PECI client device,  
and the originating agent must be capable of tolerating any code. The Pass/Fail mask  
defined in Table 6-16 applies to all codes and general response policies may be based  
on that limited information.  
6.3.5  
Originator Responses  
The simplest policy that an originator may employ in response to receipt of a failing  
completion code is to retry the request. However, certain completion codes or FCS  
responses are indicative of an error in command encoding and a retry will not result in  
a different response from the client. Furthermore, the message originator must have a  
response policy in the event of successive failure responses.  
Datasheet Volume 1 of 2  
139  
 复制成功!