Electrical Characteristics
Figure 8-14. Power Sequencing and Reset Signal Timings
PW ROK
t214
V_CPU_IO
t211
Vcc1_5_A,
Vcc1_5_B
Vcc1_1
and other
power1
Vcc3_3
t209
t213
V5REF
LAN_RST#
t305a
VccLAN3
RSM RST#
t204
t203
VccSus1_1
t202
VccSus3_3
t201
V5REF_Sus
RTCRST#
t200
VccRTC
NOTES:
1.
Other power includes VccUSBPLL, VccDMIPLL, and VccSATAPLL. All of these power signals
must independently meet the timings shown in the figure. There are no timing
interdependencies between Vcc1_1 and these other power signals. There are also no
timing interdependencies for these power signals, including Vcc1_1, to Vcc3_3 and
Vcc1_5_A/Vcc1_5_B.
2.
3.
4.
PWROK must not glitch, even if RSMRST# is low.
VccLAN includes VccLAN3_3, VccLAN1_1, and VccCL3_3.
Other power
Datasheet
285
INTEL [ INTEL ]
