Figures
Figure 1-1. Intel® G35 Express Chipset System Block Diagram Example..................19
Figure 3-1. System Address Ranges...................................................................46
Figure 3-2. DOS Legacy Address Range..............................................................47
Figure 3-3. Main Memory Address Range............................................................51
Figure 3-4. PCI Memory Address Range..............................................................53
Figure 4-1. Conceptual G Platform PCI Configuration Diagram ...............................68
Figure 4-2. Memory Map to PCI Express* Device Configuration Space.....................70
Figure 4-3. GMCH Configuration Cycle Flow Chart................................................72
Figure 9-1. System Memory Styles ..................................................................285
Figure 9-2. SDVO Conceptual Block Diagram.....................................................293
Figure 9-3. Concurrent sDVO / PCI Express* Non-Reversed Configurations............ 295
Figure 9-4. Concurrent sDVO / PCI Express* Reversed Configurations .................. 295
Figure 9-5. Intel® G35 Express Chipset System Clock Diagram............................ 308
Figure 11-1. GMCH Ballout Diagram (Top View Left – Columns 43–30) ................. 323
Figure 11-2. GMCH Ballout Diagram (Top View Middle– Columns 29–15)............... 324
Figure 11-3. GMCH Ballout Diagram (Top View Right – Columns 14–0)................. 325
Figure 11-4. GMCH Package Drawing...............................................................338
Figure 12-1. XOR Test Mode Initialization Cycles ............................................... 340
Tables
Table 3-1. Expansion Area Memory Segments.....................................................49
Table 3-2. Extended System BIOS Area Memory Segments...................................49
Table 3-3. System BIOS Area Memory Segments.................................................49
Table 3-4. Specifics of Legacy Interrupt Routing..................................................50
Table 3-5. Pre-allocated Memory Example for 64 MB DRAM, 1-MB VGA and
1-MB TSEG......................................................................................52
Table 3-6. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and
1-MB TSEG......................................................................................59
Table 3-7. SMM Space Table.............................................................................60
Table 3-8. SMM Control ...................................................................................60
Table 5-1. DRAM Controller Register Address Map (D0:F0)....................................78
Table 5-2. MCHBAR Register Address Map ........................................................113
Table 5-3. DRAM Rank Attribute Register Programming ...................................... 120
Table 5-4. EPBAR Register Address Map ...........................................................158
Table 6-1. PCI Express* Register Address Map (D1:F0) ...................................... 162
Table 7-1. DMI Register Address Map...............................................................214
Table 8-1. Integrated Graphics Device Register Address Map (D2:F0)................... 224
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1)................... 247
Table 9-1. HECI1 Register Address Map (D3:F0)................................................ 268
Table 9-1. Sample System Memory Organization with Interleaved Channels ..........284
Table 9-2. Sample System Memory Organization with Asymmetric Channels.......... 284
Table 9-3. DDR2 DIMM Supported Configurations ..............................................288
Table 9-4. DRAM Address Translation (Single Channel/Dual Asymmetric Mode)...... 289
Table 9-5. DRAM Address Translation (Dual Channel Symmetric Mode).................290
Table 9-6. Concurrent sDVO / PCI Express* Configuration Strap Controls..............294
Datasheet
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INTEL [ INTEL ]
