Features
6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 32.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
Frequency determination functionality will exist on engineering sample processors
which means that samples can run at varied frequencies. Production material will have
the bus to core ratio locked and can only be operated at the rated frequency.
Table 32.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Signal1,2
SMI#
Execute BIST
A3#
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
A25#
BR0#
A[8:4]#, A[24:11]#, A[35:26]#
NOTE:
1.
2.
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted
during RESET#.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states which may reduce
power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 22 for a visual representation of the
processor low power states.
Datasheet
87
INTEL [ INTEL ]
