Electrical Specifications
2.6.2
DC Voltage and Current Specification
Table 5.
Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit Notes2, 15
VID Range
VID
1.0000
—
1.3375
V
V
V
3
Processor Number
Core VCC
2.2 GHz
450
440
430
420
Refer to Table 6 and
Figure 1
VCC
2.0 GHz
1.8 GHz
1.6 GHz
4, 5, 6
VCC_BOOT
VCCPLL
Default VCC voltage for initial power up
PLL VCC
—
1.10
1.50
—
- 5%
+ 5%
Processor Number
ICC for
775_VR_CONFIG_06
450
440
430
420
2.2 GHz
2.0 GHz
1.8 GHz
1.6 GHz
35
35
35
35
ICC
—
—
A
7
FSB termination voltage
(DC + AC specifications)
VTT
1.14
—
1.20
—
1.26
V
mA
A
8
VTT_OUT_LEFT
and
DC Current that may be drawn from
VTT_OUT_RIGHT VTT_OUT_LEFT and VTT_OUT_RIGHT per pin
ICC
580
9
ICC for VTT supply before VCC stable
4.5
4.6
ITT
—
—
10
ICC for VTT supply after VCC stable
ICC_VCCPLL
ICC_GTLREF
I
CC for PLL land
ICC for GTLREF
NOTES:
—
—
—
—
130
200
mA
μA
1.
Unless otherwise noted, all specification in this table are based on estimates and
simulation or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
2.
3.
Adherence to the voltage specification for the processor are required to ensure reliable
processor operation.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Please note this differs from the VID employed by
the processor during a power management event (Thermal Monitor 2).
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See Section 2.3 and Table 2 for more
information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
4.
5.
6.
7.
Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a
given current. The processor should not be subjected to any VCC and ICC combination
wherein VCC exceeds VCC_MAX for a given current.
ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1f or details.
Datasheet
19
INTEL [ INTEL ]
