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313072-002 参数 Datasheet PDF下载

313072-002图片预览
型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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DDR Interface  
3.3  
Command / Address Outputs  
Two sets of DRAM command and address output pins are provided for loading and  
timing considerations. Each set drives the same DRAM commands, but the two address  
busses are inverted from each other in order to reduce power consumption and heat  
produced on the DIMM. The command and address output pin behavior is detailed  
below:  
1. Minimum address toggling. The address associated with the last command issued  
on the DRAM bus is retained during DRAM NOP/Deselect commands. The address  
and bank bits do not revert to all 1’s (or all 0’s) when the command bus is idle.  
2. Balanced bank and address busses. With some exceptions, the bank and address  
busses on the two bus copies are inverted from each other. This minimizes the  
current load on the VTT supply regulator because the balanced address bus sinks as  
much current as it sources. There are exceptions to the inversion behavior to allow  
for commands that use one or more address bits to control DRAM functionality.  
Balancing can also be disabled by setting the DRC.BALDIS register field.  
Balancing Exceptions:  
a. Address bit A10 is not balanced during all read, write, and precharge commands.  
b. No address or bank bits are balanced during any MRS and EMRS commands.  
c. Column address A0 is not balanced when the DRC.SEQADD bit is set. As with  
A10, A0 is only not balanced during read, write, and precharge commands. This  
mode is intended to work with DRAMs in sequential address mode.  
d. No address or bank bits are balanced during any command when the  
DRC.BALDIS register field is set.  
3. Balanced idle command bus. When the command bus is idle, a deselect command  
is issued with all chip selects high and all RAS/CAS/WE signals driven low on both  
command/address copies.  
4. Command/Address output control with CKE. All command and address pin outputs,  
except for ODT, CKE, and CLK, will float one DRAM clock cycle after both CKE pins  
transition from high to low. The command/address pins will be driven to valid signal  
levels on the same cycle that either CKE pin is driven from low to high.  
5. Output control during link reset. When the AMB core logic is in reset, CKE and ODT  
will be driven low, and CLK will run at normal levels and frequency. The remaining  
command/address pins will float during reset.  
6. Command/Address output control in S3 mode. When the AMB core logic is in S3  
power mode, all command/address outputs, including CKE, ODT, CLK, and all other  
command/address pins, will be driven low.  
7. CSR output control of command/address. All command/address pin outputs will  
float when the appropriate DRC bits are set. Setting the DRC.CADIS field will float  
the RAS, CAS, WE, Bank, and Address pins. DRC.CSDIS controls the chip select  
pins. DRC.ODTDIS, DRC.CKEDIS, and DRC.CLKDIS float the ODT, CKE, and clock  
pins respectively.  
26  
Intel® 6400/6402 Advanced Memory Buffer Datasheet