Registers
14.3.1.8
FBDSBCFGNXT: FBD SB Link Electrical Configuration
This register contains next settings of control bits to set link electrical parameters to
match link length and frequency characteristics.
Device:
NodeID
Function: 1
Offset:
Bit
54h
Attr
Default
Description
7:5
4:3
RV
0h
00
Reserved
RWST
SBTXDRVCUR:
‘11’ = Small
‘10’ = reserved
‘01’ = Regular
‘00’ = Large
2:1
RWST
RWST
10b
1b
SBTXDEEMP:
00 = 0 dB
01 = 3.5dB
10 = 6dB
11 = 9.5dB
0
SBRESYNCEN:
‘1’ = SB pass-thru data is in Re-sync mode
‘0’ = SB pass-thru is in Re-sample mode.
14.3.1.9
FBDNBCFGNXT: FBD NB Link Electrical Configuration
This register contains next settings of control bits to set link electrical parameters to
match link length and frequency characteristics.
Device:
NodeID
Function: 1
Offset:
Bit
55h
Attr
Default
Description
7:5
4:3
RV
0h
00
Reserved
RWST
NBTXDRVCUR:
‘11’ = Small
‘10’ = reserved
‘01’ = Regular
‘00’ = Large
2:1
RWST
RWST
10b
1b
NBTXDEEMP:
00 = 0 dB
01 = 3.5dB
10 = 6dB
11 = 9.5dB
0
NBRESYNCEN:
‘1’ = SB pass-thru data is in Re-sync mode
‘0’ = SB pass-thru is in Re-sample mode.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
175
INTEL [ INTEL ]
