Registers
14.2.4
CCR: Class Code Register
This register contains the Class Code for the AMB, specifying the device function.
Device:
Function:
Offset:
NodeID
0
09h
Bit
Attr
Default
Description
23:16
RO
RO
RO
05h
00h
00h
Base Class.
This field indicates the general device category. For the AMB, this field is hardwired
to 05h, indicating it is a “memory controller”.
15:8
7:0
Sub-Class.
This field qualifies the Base Class, providing a more detailed specification of the
device function. For the AMB, this field is hardwired to 00h, indicating it is a “RAM”.
Register-Level Programming Interface.
This field identifies a specific programming interface (if any), that device
independent software can use to interact with the device. There are no such
interfaces defined for “memory controllers”.
14.2.5
HDR: Header Type Register
This register identifies the header layout of the configuration space.
Device:
Function:
Offset:
NodeID
0
0Eh
Bit
Attr
Default
Description
7
RO
RO
1
Multi-function Device.
Selects whether this is a multi-function device, that may have alternative
configuration layouts. The AMB has more than the 256 bytes of configuration
registers allotted to a single function. Therefore, the AMB is defined to be a
multifunction device, and this bit is hardwired to 1.
6:0
00h
Configuration Layout.
This field identifies the format of the 10h through 3Fh space. The AMB uses header
type “00”: these bits are hardwired to 00h.
14.3
FBD Link Registers (Function 1)
14.3.1
FBD Link Control and Status
14.3.1.1
FBDS0: FBD Status 0
This register contains copies of status bits returned by the AMB in the most recent
northbound status frame when SYNC command R[1:0] field is 2’b00.
In the absence of SYNCs to this register, this register is not updated.
Device:
NodeID
Function: 1
Offset:
Bit
40h
Att
r
Default
Description
7:5
4
RV
RO
0h
0h
Reserved
SP: Parity: This bit contains an odd parity bit that covers the S[3:0] field.
170
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
