Introduction
1.3
Interfaces
Figure 1-1. Advanced Memory Buffer Block Diagram
Advance Memory Buffer
2/03/04
Block DIagram
10x2
10x2
NORTH
SOUTH
Southbound
Data In
Southbound
Data Out
Data Merge
Re-Time
Re-synch
PLL
1x2
demux
10*12
PISO
mux
Ref Clock
10*12
Reset#
Link Init SM
and Control
and CSRs
Reset
Reset
Control
s
Init
patterns
4
4
DRAM Clock
DRAM Clock
IBIST - RX
LAI Logic
IBIST - TX
#
Command
Decoder &
CRC Check
failover
29
29
Cmd Out
DRAM Address
Command Copy
/
1
DRAM Cmd
Thermal
Sensor
DRAM Address
Command Copy
/
2
DDR State
Controller
and CSRs
Data Out
Core Control
and CSRs
36
deep
Write
Data
FIFO
72
+ 18x2
DRAM
Data / Strobe
External MEMBIST
DDR Calibration &
DDR IOBIST/DFX
Data In
LAI
Controller
Data CRC Gen
& Read FIFO
Sync & Idle
Pattern
NB LAI Buffer
Generator
IBIST - RX
IBIST - TX
SMBus
SMbus
Controller
mux
Link Init SM
and Control
and CSRs
failover
14*12
14*6*2
PISO
demux
Re-synch
Re-Time
Data Merge
Northbound
Data In
Northbound
Data Out
14x2
14x2
Figure 1-2 illustrates the AMB and all of its interfaces. They consist of two FBD links,
one DDR2 channel, and an SMBus interface. Each FBD link connects the AMB to a host
memory controller or an adjacent FBD. The DDR2 channel supports direct connection to
the DDR2 SDRAMs on a Fully Buffered DIMM.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
13
INTEL [ INTEL ]
