Electrical Specifications
Table 2-3.
Voltage Identification Definition (Sheet 2 of 2)
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
VID4 VID3 VID2 VID1 VID0 VID5 VCC_MAX
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1
OFF
1
OFF
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
Notes:
1.
2.
When this VID pattern is observed, the voltage regulator output should be disabled.
Shading denotes the expected VID range of the Dual-Core Intel Xeon Processor 5000 series [1.0750 V -
1.3500 V].
Table 2-4.
Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1
LL_ID0
Description
0
0
1
1
0
1
0
1
Reserved
Dual-Core Intel Xeon Processor 5000 Series
Reserved
Reserved
Note:
1.
2.
3.
4.
The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
These signals are not connected to the processor die.
A logic 0 is achieved by pulling the signal to ground on the package.
A logic 1 is achieved by leaving the signal as a no connect on the package.
Table 2-5.
Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1
MS_ID0
Description
0
0
1
1
0
1
0
1
Dual-Core Intel Xeon Processor 5000 Series
Reserved
Reserved
Reserved
20
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
INTEL [ INTEL ]
