Features
Figure 6-1. Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Extended HALT or HALT
State
- BCLK running
- Snoops and interrupts
allowed
Normal State
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
- Normal Execution
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Extended HALT Snoop or
HALT Snoop State
- BCLK running
- Service Snoops to caches
Extended Stop Grant
State or Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Extended Stop Grant
Snoop or Stop Grant
Snoop State
- BCLK running
- Service Snoops to caches
Snoop Event Occurs
Snoop Event Serviced
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification. Refer to the Conroe Processor Family BIOS Writer's Guide (BWG) for
Extended HALT configuration information.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the following sections for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted; however, the other processor continues normal operation.
The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.
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Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
INTEL [ INTEL ]
