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298643-012 参数 Datasheet PDF下载

298643-012图片预览
型号: 298643-012
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔®奔腾® 4处理器至尊版支持超线程技术 [Intel Pentium 4 Processor Extreme Edition Supporting Hyper-Threading Technology]
分类和应用:
文件页数/大小: 85 页 / 1758 K
品牌: INTEL [ INTEL ]
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Electrical Specifications  
2.7  
Asynchronous GTL+ Signals  
The Pentium 4 processor on 0.13 micron process does not use CMOS voltage levels on any signals  
that connect to the processor. As a result, legacy input signals (such as A20M#, IGNNE#, INIT#,  
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK#) use GTL+ input buffers.  
Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers.  
PROCHOT# uses GTL+ input/output buffer. All of these signals follow the same DC requirements  
as AGTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1  
transition) by the processor (the major difference between GTL+ and AGTL+). These signals do  
not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the  
Asynchronous GTL+ signals are required to be asserted for at least two BCLKs for the processor to  
recognize them. See Section 2.11 for the DC specifications for the Asynchronous GTL+ signal  
groups. See Section 6.2 for additional timing requirements for entering and leaving the low power  
states.  
2.8  
2.9  
Test Access Port (TAP) Connection  
Because of the voltage levels supported by other components in the Test Access Port (TAP) logic,  
it is recommended that the Pentium 4 processor on 0.13 micron process be first in the TAP chain  
and followed by any other components within the system. A translation buffer should be used to  
connect to the rest of the chain unless one of the other components is capable of accepting an input  
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#.  
Two copies of each signal may be required, with each driving a different voltage level.  
System Bus Frequency Select Signals (BSEL[1:0])  
The BSEL[1:0] are output signals used to select the frequency of the processor input clock  
(BCLK[1:0]). Table 2-4 defines the possible combinations of the signals, and the frequency  
associated with each combination. The required frequency is determined by the processor, chipset,  
and clock synthesizer. All agents must operate at the same frequency.  
The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process currently operates at a  
400 MHz, 533 MHz, or 800 MHz system bus frequency. The Pentium 4 processor Extreme Edition  
supporting Hyper-Threading Technology currently operates at 800 MHz system bus frequency.  
Individual processors will operate only at their specified system bus frequency.  
For more information about these pins, refer to Section 4.2 and the appropriate platform design  
guidelines.  
Table 2-4. BSEL[1:0] Frequency Table for BCLK[1:0]  
BSEL1  
BSEL0  
Function  
L
L
L
H
L
100 MHz  
133 MHz  
H
H
200 MHz  
H
RESERVED  
22  
Intel® Pentium® 4 Processor on 0.13 Micron Process Datasheet