1-Gbit P30 Family
Appendix B Flowcharts
Figure 40.
Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Start
Command
Operation
Comments
Program Data = 0x40
Setup Addr = Location to program
Write
Write 0x40,
(Setup)
Word Address
Data = Data to program
Addr = Location to program
Write
Read
Data
Write Data,
(Confirm)
Word Address
None
Status register data
Program
Suspend
Loop
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle
None
No
Suspend?
Yes
0
SR[7] =
1
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Full Status
Check
(if desired)
Write 0xFF after the last operation to set to the Read Array
state.
Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Error
Idle
Idle
None
1
1
1
VPP Range
Error
SR[3] =
0
Check SR[4]:
1 = Data Program Error
None
Program
Error
Check SR[1]:
1 = Block locked; operation aborted
SR[4] =
0
Idle
None
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Device
Protect Error
SR[1] =
0
Program
Successful
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
85
INTEL [ INTEL ]
