1-Gbit P30 Family
11.3.1
BEFP Requirements and Considerations
BEFP requirements:
• Case temperature: TC = 25 °C ± 5 °C
• VCC within specified operating range
• VPP driven to VPPH
• Target block unlocked before issuing the BEFP Setup and Confirm commands
• The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired
• WA0 must align with the start of an array buffer boundary1
BEFP considerations:
• For optimum performance, cycling must be limited below 100 erase cycles per block2
• BEFP programs one block at a time; all buffer data must fall within a single block3
• BEFP cannot be suspended
• Programming to the flash memory array can occur only when the buffer is full4
NOTES:
1.
2.
3.
4.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start
point is A[4:0] = 0x00.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7]
(Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks
(Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and BEFP operation
terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred
due to an incorrect VPP level.
Note:
Reading from the device after the BEFP Setup and Confirm command sequence outputs Status
Register data. Do not issue the Read Status Register command; it will be interpreted as data to be
loaded into the buffer.
11.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to
determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device
is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is
available.
April 2005
64
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
