Intel StrataFlash® Wireless Memory (L18)
Revision History
Revision Date Revision
Description
10/15/02
01/20/03
-001
-002
Initial Release
Revised 256-Mbit Partition Size
Revised 256-Mbit Memory Map
Change WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all
Writes)
Change WAIT function to active during Synchronous Non-Array Read
Updated all Waveforms to reflect new WAIT function
Revised Section 8.2.2
Added Synchronous Read to Write transition Section
Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns
Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22
Various text edits
04/11/03
08/04/03
-003
-004
Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing
Changed I
and I
values
CCR
CCS
Added 256-Mbit AC Speed
Changed Program and Erase Spec
Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow
Chart
Revised Read While Buffered Programming Flow Chart
Revised Appendix A Write State Machine
Revised CFI Table 21 CFI Identification
Various text edits.
01/20/04
05/22/04
-005
-006
Various text clarifications, various text edits, block locking state diagram clarification, synchronous
read to write timing clarification, write to synchronous read timing clarification
Minor text edits
Changed Capacitance values
Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and
Automatic Power Savings Current (typ)
Updated Transient Equialent Testing Load Circuit
April 2005
6
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
INTEL [ INTEL ]
