Intel StrataFlash® Wireless Memory (L18)
7.6
AC Write Specifications
Nbr.
Symbol
Parameter (1, 2)
Min
Max
Units
Notes
W1
W2
tPHWL RST# high recovery to WE# low
tELWL CE# setup to WE# low
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
W3
tWLWH WE# write pulse width low
tDVWH Data setup to WE# high
tAVWH Address setup to WE# high
tWHEH CE# hold from WE# high
tWHDX Data hold from WE# high
tWHAX Address hold from WE# high
tWHWL WE# pulse width high
50
50
50
0
W4
W5
W6
1,2
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
W16
tVPWH
tQVVL
V
V
setup to WE# high
PP
PP
1,2,3,7
hold from Status read
tQVBL WP# hold from Status read
tBHWH WP# setup to WE# high
tWHGL WE# high to OE# low
tWHQV WE# high to read valid
0
1,2,3,7
1,2,9
200
0
t
+ 35
ns 1,2,3,6,10
AVQV
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid
0
-
ns
1,2,3,6
Write to Synchronous Read Specifications
W19 tWHCH/L WE# high to Clock valid
19
19
-
-
ns
ns
1,2,3,6,10
W20
tWHVH WE# high to ADV# high
Write Specifications with Clock Active
W21
W22
tVHWL ADV# high to WE# low
tCHWL Clock high to WE# low
-
-
20
20
ns
ns
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE#
WLWH
ELEH
or WE# high (whichever occurs first). Hence, t
= t
= t
= t
.
WLWH
ELEH
WLEH
ELWH
5.
Write pulse width high (t
or t
) is defined from CE# or WE# high (whichever occurs first) to
WHWL
EHEL
CE# or WE# low (whichever occurs last). Hence, t
= t
= t
= t
).
EHWL
WHWL
EHEL
WHEL
6.
7.
8.
tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
V
PP
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
10.
11.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read
operation to reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
37
INTEL [ INTEL ]
