28F400BX-T/B, 28F004BX-T/B
1.6 28F004BX Pin Descriptions
Symbol
A –A
Type
I
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
0
18
A
I
ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this
9
mode A decodes between the manufacturer and device ID’s.
9
0
Ý
Ý
DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Inputs commands to the command user interface when
DQ –DQ
0
I/O
7
Ý
Ý
CE and WE are active. Data is internally latched during the write and program
cycles. Outputs array, Intelligent Identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.
Ý
Ý
CE
RP
I
I
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
Ý
Ý
sense amplifiers. CE is active low; CE high deselects the memory device and
Ý
Ý
reduces power consumption to standby levels. If CE and RP are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
Ý
Ý
CE and RP input stages.
RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
Ý
When RP is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
e
Ý
When RP
or erased.
11.4V minimum the Boot Block is unlocked and can be programmed
Ý
When RP is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power transitions.
Ý
When RP transitions from logic low to logic high, the flash memory enters the
read-array mode.
Ý
OE
I
I
OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a
Ý
read cycle. OE is active low.
Ý
Ý
WE
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
Ý
is active low. Addresses and data are latched on the rising edge of the WE pulse.
V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
PP
k
NOTE: V
PP
V
memory contents cannot be altered.
PPLMAX
g
g
DEVICE POWER SUPPLY (5V 10%, 5V 5%)
V
CC
GND
NC
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
DON’T USE PIN: Pin should not be connected to anything.
DU
10
INTEL [ INTEL ]
