28F200BX-T B 28F002BX-T B
1 6 Pin Descriptions for x8 28F002BX
Symbol
A
0
–A
17
A
9
DQ
0
–DQ
7
Type
I
I
I O
Name and Function
ADDRESS INPUTS
for memory addresses Addresses are internally latched during
a write cycle
ADDRESS INPUT
When A
9
is at 12V the signature mode is accessed During this
mode A
0
decodes between the manufacturer and device ID’s
DATA INPUTS OUTPUTS
Inputs array data on the second CE and WE cycle
during a program command Inputs commands to the command user interface
when CE and WE are active Data is internally latched during the write and
program cycles Outputs array Intelligent Identifier and status register data The
data pins float to tri-state when the chip is deselected or the outputs are disabled
CHIP ENABLE
Activates the device’s control logic input buffers decoders and
sense amplifiers CE is active low CE high deselects the memory device and
reduces power consumption to standby levels If CE and RP are high but not at
a CMOS high level the standby current will increase due to current flow through the
CE and RP input stages
RESET DEEP POWERDOWN
Provides Three-State control Puts the device in
deep powerdown mode Locks the Boot Block from program erase
When RP is at logic high level and equals 6 5V maximum the Boot Block is locked
and cannot be programmed or erased
When RP
e
11 4V minimum the Boot Block is unlocked and can be programmed
or erased
When RP is at a logic low level the Boot Block is locked the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased therefore providing data protection during power
transitions When RP transitions from logic low to logic high the flash memory
enters the read-array mode
OUTPUT ENABLE
Gates the device’s outputs through the data buffers during a
read cycle OE is active low
WRITE ENABLE
Controls writes to the Command Register and array blocks WE
is active low Addresses and data are latched on the rising edge of the WE pulse
PROGRAM ERASE POWER SUPPLY
For erasing memory array blocks or
programming data in each block
Note
V
PP
k
V
PPLMAX
memory contents cannot be altered
DEVICE POWER SUPPLY (5V
g
10% 5V
g
5%)
GROUND
For all internal circuitry
NO CONNECT
Pin may be driven or left floating
DON’T USE PIN
Pin should not be connected to anything
CE
I
RP
I
OE
WE
V
PP
I
I
V
CC
GND
NC
DU
9
INTEL [ INTEL CORPORATION ]
