E
1.0
1.1
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
INTRODUCTION
1.2
Main Features
This datasheet comprises the specifications for
the 28F002BC 2-Mbit flash memory. Section 1
provides an overview of the 2-Mbit flash memory,
including
applications,
pinouts,
and
pin
descriptions. Section 2 describes the memory
organization in detail. Section 3 defines a
description of the memory’s principles of
operation. Finally, Section 4 details the memory’s
operating specifications.
The 28F002BC Boot Block flash memory is a high-
performance, 2-Mbit (2,097,152 bit) flash memory
organized as 256 Kbytes (262,144 bytes) of 8 bits
each.
The 28F002BC has separately erasable blocks,
including a hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes each)
and two main blocks (one block of 98,304 bytes
and one block of 131,072 bytes). An erase
operation typically erases one of the main blocks
in 2.4 seconds and the boot or parameter blocks in
1.0 second. Each block can be independently
erased and programmed 100,000 times.
The boot block is located at the top of the address
map to match the protocol of many systems,
including Intel’s MCS-186 family, 80960CA, i860™
microprocessors as well as Pentium and Pentium
Pro microprocessors. The hardware-lockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code
required for booting-up a system. When the RP#
pin is between 11.4V and 12.6V, the boot block is
unlocked and program and erase operations can
be performed. When the RP# pin is at or below
6.5V, the boot block is locked and program and
erase operations to the boot block are ignored.
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
28F002BC.
Program and Erase Automation allows program
and erase operations to be executed using an
industry standard two-write command sequence to
the CUI. Data writes are performed in byte
increments. Each byte in the flash memory can be
programmed independently of other memory
locations but is erased simultaneously with all
other locations within the block.
The status register (SR) indicates the status of the
internal Write State Machine (WSM), which reports
critical information on program and/or erase
sequences.
The maximum access time of 80 ns (t
ACC
) is
guaranteed over the commercial temperature
range (0°C to +70°C), 10% V
CC
supply voltage
range (4.5V to 5.5V) and 100 pF output load.
Designing for Density
Upgradeability
The 28F002BC has been optimized to meet
market requirements. Applications currently using
the 28F001BX and 28F002BX can migrate to this
product. Of course, both the 28F001BX and the
28F002BX devices use an 8-bit wide bus. Those
applications needing a 16-bit wide bus or lower
voltage can convert to the Smart 5 or
SmartVoltage family of flash memory products.
SmartVoltage is also the natural migration path to
the 4-Mbit density. Both the 28F002BC and the
4-Mbit SmartVoltage are offered in identical
packages to make upgrade seamless. A few
simple considerations can smooth the migration
path significantly:
1.
Connect the NC pin of the 28F002BC to GND
(this will retain boot block locking when a
4-Mbit SmartVoltage is inserted).
Design a switchable V
PP
to take advantage of
the 5V V
PP
option on SmartVoltage devices.
If anticipating to use the 5V V
PP
option,
switch V
PP
to GND for complete write
protection.
2.
3.
Previous designs with Intel’s 28F002BX devices
on occasion had to use a NOR gate (or some
other scheme) to prevent issues with floating
addresses latching incorrect data. The 28F002BC
has corrected this issue and does not need the
NOR gate. When migrating a design using the
28F002BX to the 28F002BC, the NOR gate can be
removed. When considering upgrading, packaging
is of paramount importance. Current and future
market trends indicate TSOP and PSOP as the
packages that will enable designs into the next
century.
PRELIMINARY
5
INTEL [ INTEL CORPORATION ]
