E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
3.2.1 READ ARRAY
with altering memory contents are accessible via
the CUI.
When RP# transitions from VIL (reset) to VIH, the
device will be in read array mode and will respond
to the read control inputs (CE#, OE#, and address
inputs) without any commands being written to the
CUI.
The purpose of the Write State Machine (WSM) is
to automate the write and erasure of the device
completely. The WSM will begin operation upon
receipt of a signal from the CUI and will report
status back through the status register. The CUI will
handle the WE# interface to the data and address
latches, as well as system software requests for
status while the WSM is in operation.
When the device is in read array mode, four control
signals must be manipulated to read data at the
outputs.
•
•
•
•
WE# must be logic high (VIH
CE# must be logic low (VIL)
OE# must be logic low (VIL)
)
3.1
Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in
Tables 2 and 4.
RP# must be logic high (VIH
)
In addition, the address of the desired location must
be applied to the address pins. Refer to AC
Characteristics for the exact sequence and timing
of these signals.
3.2
Read Operations
If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to the
CUI before array reads can take place.
The 28F002BC has three user read modes: read
array, read intelligent identifier, and read status
register.
During power-up conditions, it takes a maximum of
600 ns from when VCC is at 4.5V to when valid data
is available at the outputs.
Table 2. 28F002BC Bus Operations
Mode
Notes RP#
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIH
X
A9
X
A0
X
VPP
X
DQ0–7
DOUT
High Z
High Z
High Z
89H
Read
1,2,3
VIH
VIH
VIH
VIL
VIH
VIH
VIH
Output Disable
X
X
X
Standby
X
X
X
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
8
4
X
X
X
X
X
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VID
VID
X
VIL
VIH
X
X
4
X
7CH
5,6,7
VPPH
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP
.
3. See DC Characteristics for VPPLK, VPPH, VHH, VID voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A -A17 = X.
1
5. Refer to Table 3 for valid DIN during a write operation.
6. Command writes for program or block erase are only executed when VPP = VPPH
.
7. To write or erase the boot block, hold RP# at VHH
.
8. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
13
PRELIMINARY
INTEL [ INTEL ]
