Intel® Celeron® Processor up to 1.10 GHz
Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)
T# Parameter
V1’: BCLK VIL
Min
Nom
Max
Unit
Figure
Notes
0.5
V
V
V
V
V
V
V
12
12
12
12
12
12
12
V2’: BCLK VIH
2.0
–0.5
2.0
V3’: VIN Absolute Voltage Range
V4’: Rising Edge Ringback
V5’: Falling Edge Ringback
V6’: Tline Ledge Voltage
V7’: Tline Ledge Oscillation
3.3
2
3
3
0.5
1.7
0.2
1.0
At Ledge Midpoint 4
Peak-to-Peak 5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
guideline is an absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The
midpoint voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.
Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
T3
V3
V4
V2
V7
V6
V1
V5
V3
T6
T4
T5
54
Datasheet
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