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243658-020 参数 Datasheet PDF下载

243658-020图片预览
型号: 243658-020
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔赛扬处理器高达1.10 GHz的 [Intel Celeron Processor up to 1.10 GHz]
分类和应用:
文件页数/大小: 128 页 / 2501 K
品牌: INTEL [ INTEL ]
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Intel® Celeron® Processor up to 1.10 GHz  
2.7.1  
2.7.2  
Asynchronous Vs. Synchronous for System Bus Signals  
All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be  
applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals  
are synchronous to TCK.  
System Bus Frequency Select Signal (BSEL[1:0])  
The BSEL pins have two functions. First, they can act as outputs and can be used by an external  
clock generator to select the proper system bus frequency. Second, they can act as an inputs and  
can be used by a system BIOS to detect and report the processor core frequency. See the Intel®  
Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126) for  
an example implementation of BSEL.  
BSEL0 is 3.3 V tolerant for the S.E.P. Package, while it is 2.5 V tolerant on the PPGA package. A  
logic-low on BSEL0 is defined as 66 MHz. On the FC-PGA/FC-PGA2 packages a logic low on  
both BSEL0 and BSEL1 are defined as 66 MHz and are 3.3V tolerant.  
2.8  
Test Access Port (TAP) Connection  
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is  
recommended that the Celeron processor be first in the TAP chain and followed by any other  
components within the system. A translation buffer should be used to connect to the rest of the  
chain unless one of the other components is capable of accepting a VccCMOS (1.5V or 2.5 V) input.  
Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may  
be required with each driving a different voltage level.  
A Debug Port may be placed at the start and end of the TAP chain with the TDI of the first  
component coming from the Debug Port and the TDO from the last component going to the Debug  
Port.  
2.9  
Maximum Ratings  
Table 4 contains the Celeron processor stress ratings only. Functional operation at the absolute  
maximum and minimum is not implied nor guaranteed. The processor should not receive a clock  
while subjected to these conditions. Functional operating conditions are given in the AC and DC  
tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore,  
although the processor contains protective circuitry to resist damage from static electric discharge,  
one should always take precautions to avoid high static voltages or electric fields.  
Datasheet  
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