Introduction
1
The 21152 is a second-generation PCI-to-PCI bridge and is fully compliant with
PCI Local Bus
Specification, Revision 2.1.
The 21152 is pin-to-pin compatible with the 21052, which is fully
compliant with
PCI Local Bus Specification, Revision 2.0.The
21152 provides full support for
delayed transactions, enabling buffering of memory read, I/O, and configuration transactions. The
21152 has separate posted write, read data, and delayed transaction queues with significantly more
buffering capability than first-generation bridges. In addition, the 21152 supports bi-directional
buffering of simultaneous multiple posted write and delayed transactions.Among the features
provided by the 21152 are a programmable 2-level secondary bus arbiter, individual secondary
clock software control, and enhanced address decoding. The 21152 has sufficient clock and
arbitration pins to support four PCI bus master devices directly on its secondary interface.
The 21152 allows the two PCI buses to operate concurrently. This means that a master and a target
on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may
increase system performance in applications such as multimedia.
1.1
Features
The 21152 has the following features:
•
•
•
•
•
Complies fully with
Revision 2.1
of the
PCI Local Bus Specification,
Complies fully with
Revision 1.1
of the
PCI-to-PCI Bridge Architecture Specification,
Complies fully with the
Advanced Configuration Power Interface
(ACPI)
Specification
Complies fully with the
PCI Power Management Specification,
Revision 1.0
1
Implements delayed transactions for all PCI configuration, I/O, and memory read
commands—up to three transactions simultaneously in each direction
direction—up to three transactions simultaneously in each direction
•
Allows 88 bytes of buffering (data and address) for posted memory write commands in each
•
Allows 72 bytes of read data buffering in each direction
•
Provides concurrent primary and secondary bus operation to isolate traffic
•
Provides five secondary clock outputs
— Low skew, permitting direct drive of option slots
— Individual clock control through configuration space
•
Provides arbitration support for four secondary bus devices
— A programmable 2-level arbiter
— Hardware disable control, permitting use of an external arbiter
•
Provides enhanced address decoding
— A 32-bit I/O address range
1. 21152–AB and later revisions only. The 21152–AA does not implement this feature.
21152 PCI-to-PCI Bridge Preliminary Datasheet
1-1
INTEL [ INTEL CORPORATION ]
