21143 PCI/CardBus 10/100 Ethernet LAN
Controller
Networking Silicon
Preliminary
Datasheet
Product Features
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Fully compliant with Revision 2.1 of the
PCI Local Bus Specification
and with
Revision 1.0 of the
PCI Bus Power
Management Interface Specification.
Fully compliant with Revision 1.0 of the
Advanced Configuration and Power
Interface
(ACPI)
Specification
and with
Revision 1.0 of the
Network Device Class
Power Management Specification,
under
the OnNow Architecture for Microsoft’s
PC 97 Hardware Design Guide
and
PC 98
System Design Guide.
Supports IEEE 802.3 with full
Auto-Negotiation algorithm of full-duplex
and half-duplex operation for 10 Mb/s and
100 Mb/s (NWAY).
Supports IEEE 802.3 and ANSI 8802-3
Ethernet standards.
Supports direct memory access (DMA) and
has direct interface to both the CardBus*
and PCI local bus.
Provides glueless 32-bit PCI bus master
interface.
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Contains large independent receive and
transmit FIFOs.
Contains internal PCS and scrambler/
descrambler for MII/SYM interface for
100BASE-TX.
Contains onchip integrated AUI port and a
10BASE-T transceiver.
Supports autodetection between
10BASE-T, AUI, and MII/SYM ports.
Provides an upgradable boot ROM
interface up to 256KB.
Supports remote wake-up-LAN and Magic
Packet* with the SecureON™ password
option.
Supports PCI/CardBus clock speed
frequency from dc to 33 MHz; network
operation with PCI clock from 20 MHz to
33 MHz.
Implements low-power management with
two power-saving modes (sleep and
snooze).
Implements low-power, 3.3-V CMOS
technology.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 278073-001
November 1998
INTEL [ INTEL CORPORATION ]
