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10M25SCE144C8G 参数 Datasheet PDF下载

10M25SCE144C8G图片预览
型号: 10M25SCE144C8G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 25000-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, EQFP-144]
分类和应用: 时钟可编程逻辑
文件页数/大小: 68 页 / 976 K
品牌: INTEL [ INTEL ]
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M10-DATASHEET  
2015.05.04  
10  
OCT Variation after Calibration at Device Power-Up  
The definitions for equation are as follows:  
T1 is the initial temperature.  
T2 is the final temperature.  
MF is multiplication factor.  
Rinitial is initial resistance.  
Rfinal is final resistance.  
Subscript x refers to both V and T.  
∆RV is variation of resistance with voltage.  
∆RT is variation of resistance with temperature.  
dR/dT is the change percentage of resistance with temperature after calibration at device power-up.  
dR/dV is the change percentage of resistance with voltage after calibration at device power-up.  
V1 is the initial voltage.  
V2 is final voltage.  
The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.  
Figure 2: Example for OCT Resistance Calculation after Calibration at Device Power-Up  
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MAX 10 FPGA Device Datasheet  
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Altera Corporation