10M25SCE144A7G 参数 Datasheet PDF下载

M10-DATASHEET

2015.05.04

Bus Hold Parameters

7

10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on.

Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is

enabled or disabled. This is applicable to all MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50

devices. The ADC I/O pins are in Bank 1A.

Table 10: I/O Pin Leakage Current for MAX 10 Devices—Preliminary

Symbol

Parameter

Condition

Min

Max

Unit

I

I

I

OZ

Input pin leakage current

Tristated I/O pin leakage current

V

I

= 0 V to V

CCIOMAX

V

O

= 0 V to V

CCIOMAX

–10

–10

10

10

µA

µA

Bus Hold Parameters

Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option

to enable bus hold in user mode. Bus hold is always disabled in configuration mode.

Table 11: Bus Hold Parameters for MAX 10 Devices—Preliminary

V

CCIO

(V)

Parameter

Condition

Min

1.2

Max

Min

1.5

Max

Min

1.8

Max

Min

2.5

Max

Min

3

Max

Min

3.3

Max

Unit

Bus-hold low,

sustaining current

Bus-hold high,

sustaining current

Bus-hold low,

overdrive current

Bus-hold high,

overdrive current

Bus-hold trip point

V

IN

> V

IL

(maximum)

V

IN

< V

IL

(minimum)

0 V < V

IN

<

V

CCIO

0 V < V

IN

<

V

CCIO

—

8

–8

—

—

0.3

—

—

125

–125

0.9

12

–12

—

—

0.375

—

—

175

–175

1.125

30

–30

—

—

0.68

—

—

200

–200

1.07

50

–50

—

—

0.7

—

—

300

–300

1.7

70

–70

—

—

0.8

—

—

500

–500

2

70

–70

—

—

0.8

—

—

500

–500

2

µA

µA

µA

µA

V

MAX 10 FPGA Device Datasheet

Altera Corporation