M10-DATASHEET
2015.05.04
67
Document Revision History for MAX 10 FPGA Device Datasheet
Changes
Date
Version
December 2014
2014.12.15
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Restructured Programming/Erasure Specifications for MAX 10 Devices table to add temperature specifica‐
tions that affect the data retention duration.
Added statements in the I/O Pin Leakage Current section: Input channel leakage of ADC I/O pins due to
hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled
or disabled. This is applicable to all MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16,
10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.
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Added a statement in the I/O Standards Specifications section: You must perform timing closure analysis to
determine the maximum achievable frequency for general purpose I/O standards.
Updated SSTL-2 Class I and II I/O standard specifications for JEDEC compliance as follows:
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VIL(AC) Max: Updated from VREF – 0.35 to VREF – 0.31
VIH(AC) Min: Updated from VREF + 0.35 to VREF + 0.31
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Added a note to BLVDS in Differential I/O Standards Specifications for MAX 10 Devices table: BLVDS TX
is not supported in single supply devices.
Added a link to MAX 10 High-Speed LVDS I/O User Guide for the list of I/O standards supported in single
supply and dual supply devices.
Added a statement in PLL Specifications for MAX 10 Single Supply Device table: For V36 package, the PLL
specification is based on single supply devices.
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Added Internal Oscillator Specifications from MAX 10 Clocking and PLL User Guide.
Added UFM specifications for serial interface.
Updated total harmonic distortion (THD) specifications as follows:
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Single supply devices: Updated from 65 dB to –65 dB
Dual supply devices: Updated from 70 dB to –70 dB (updated from 65 dB to –65 dB for dual function
pin)
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Added condition for On-Chip Temperature Sensor—Absolute accuracy parameter in ADC Performance
Specifications for MAX 10 Dual Supply Devices table. The condition is: with 64 samples averaging.
Updated the description in Periphery Performance Specifications to mention that proper timing closure is
required in design.
Updated HSIODR and fHSCLK specifications for x10 and x7 modes in True LVDS Transmitter Timing
Specifications for MAX 10 Dual Supply Devices.
MAX 10 FPGA Device Datasheet
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