M10-DATASHEET
2015.05.04
66
Document Revision History for MAX 10 FPGA Device Datasheet
Date
Version
Changes
•
Updated tx Jitter specifications in the following tables:
•
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
•
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
•
•
Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
•
•
True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
•
•
•
•
Updated SW specifications in LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices
table.
Added a note to tx Jitter for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O
switching noise.
Updated the description for tLOCK for all LVDS tables: Time required for the PLL to lock, after CONF_DONE
signal goes high, indicating the completion of device configuration.
Updated Memory Output Clock Jitter Specifications section.
•
•
Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.
Updated PLL output routing from global clock network to PHY clock network.
•
•
Added I/O Timing for MAX 10 Devices table.
Added VHYS in the Glossary table.
January 2015
2015.01.23
•
•
Removed a note to VCCA in Power Supplies Recommended Operating Conditions for MAX 10 Dual Supply
Devices table. This note is not valid: All VCCA pins must be connected together for EQFP package.
Corrected the maximum value for tOUTJITTER_CCJ_ IO (FOUT ≥ 100 MHz) from 60 ps to 650 ps in PLL Specifi‐
cations for MAX 10 Devices table.
MAX 10 FPGA Device Datasheet
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