M10-DATASHEET
2015.05.04
65
Document Revision History for MAX 10 FPGA Device Datasheet
Changes
Date
Version
•
Updated fHSCLK and HSIODR specifications for –A7 speed grade in the following tables:
•
•
•
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
•
•
•
•
True LVDS Transmitter Timing Specifications for MAX 10 Single Supply Devices
True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices
Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
•
•
LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for MAX 10 Dual Supply
Devices
•
Updated TCCS specifications in the following tables:
•
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
•
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply
Devices
•
•
Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
•
•
•
•
True LVDS Transmitter Timing Specifications for MAX 10 Single Supply Devices
True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices
Emulated LVDS_E_3R Transmitter Timing Specifications for MAX 10 Single Supply Devices
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual
Supply Devices
MAX 10 FPGA Device Datasheet
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