M10-DATASHEET
2015.05.04
61
Glossary
Term
Definition
RSKM (Receiver input skew
margin)
HIGH-SPEED I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM =
(TUI – SW – TCCS) / 2.
Sampling window (SW)
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The
setup and hold times determine the ideal strobe position in the sampling window.
Single-ended voltage referenced
I/O standard
The AC input signal values indicate the voltage levels at which the receiver must meet its timing specifications.
The DC input signal values indicate the voltage levels at which the final logic state of the receiver is unambigu‐
ously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is
intended to provide predictable receiver timing in the presence of input waveform ringing.
tC
High-speed receiver/transmitter input and output clock period.
TCCS (Channelto- channel-
skew)
HIGH-SPEED I/O block: The timing difference between the fastest and slowest output edges, including tCO
variation and clock skew. The clock is included in the TCCS measurement.
tcin
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
tCO
tcout
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
tDUTY
tFALL
tH
Timing Unit Interval (TUI)
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
tOUTJITTER_DEDCLK
tOUTJITTER_IO
tpllcin
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
Signal low-to-high transition time (20–80%).
tpllcout
tRISE
MAX 10 FPGA Device Datasheet
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