M10-DATASHEET
2015.05.04
60
Programmable IOE Delay for Column Pins
Programmable IOE Delay for Column Pins
Table 53: IOE Programmable Delay on Column Pins for MAX 10 Devices—Preliminary
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of
the Quartus II software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
Maximum Offset
Number
Minimum
Offset
Parameter
Paths Affected
of
Fast Corner
Slow Corner
Unit
Settings
–I7
–C8
–C7
–C8
–I7
–A7
Input delay from pin Pad to I/O
7
8
2
0
0
0
0.777
0.877
0.417
0.833
1.73
1.79
2.017
0.973
1.788
1.666
ns
ns
ns
to internal cells
dataout to core
Input delay from pin Pad to I/O
0.942
0.447
1.951
0.931
2.018
0.961
1.882
0.887
to input register
input register
I/O output
Delay from output
register to output pin register to pad
Glossary
Table 54: Glossary
Term
Definition
Preliminary
Some tables show the designation as “Preliminary”. Preliminary characteristics are created using simulation
results, process data, and other known parameters.
Final numbers are based on actual silicon characterization and testing. The numbers reflect the actual perform‐
ance of the device under worst-case silicon process, voltage, and junction temperature conditions. There are no
preliminary designations on finalized tables.
RL
Receiver differential input discrete resistor (external to MAX 10 devices).
MAX 10 FPGA Device Datasheet
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