M10-DATASHEET
2015.05.04
59
Programmable IOE Delay
Table 51: I/O Timing for MAX 10 Devices—Preliminary
These I/O timing parameters are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate for 10M08DAF484 device.
Symbol
Parameter
–C7, –I7
–0.750
1.180
–C8
–0.808
1.215
5.575
5.467
Unit
Tsu
Global clock setup time
Global clock hold time
ns
Th
ns
Tco
Tpd
Global clock to output delay
5.131
ns
Best case pin-to-pin propagation delay through one LUT
4.907
ns
Programmable IOE Delay
Programmable IOE Delay On Row Pins
Table 52: IOE Programmable Delay on Row Pins for MAX 10 Devices—Preliminary
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of
the Quartus II software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
Maximum Offset
Number
Minimum
Offset
Parameter
Paths Affected
of
Fast Corner
Slow Corner
Unit
Settings
–I7
–C8
–C7
–C8
–I7
–A7
Input delay from pin Pad to I/O
7
8
2
0
0
0
0.782
0.887
0.460
0.838
1.738
1.799
2.040
1.073
1.796
1.673
ns
ns
ns
to internal cells
dataout to core
Input delay from pin Pad to I/O
0.953
0.493
1.973
1.027
2.042
1.061
1.902
0.977
to input register
input register
I/O output
Delay from output
register to output pin register to pad
MAX 10 FPGA Device Datasheet
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