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10M04SAU169C8G 参数 Datasheet PDF下载

10M04SAU169C8G图片预览
型号: 10M04SAU169C8G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 时钟可编程逻辑
文件页数/大小: 68 页 / 976 K
品牌: INTEL [ INTEL CORPORATION ]
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6
Programming/Erasure Specifications
M10-DATASHEET
2015.05.04
Symbol
Parameter
Condition
Min
Max
Unit
V
O
T
J
Output voltage for I/O pins
Operating junction temperature
Commercial
Industrial
Automotive
Standard POR
(6)
0
0
–40
–40
200 μs
200 μs
200 μs
V
CCIO
85
100
125
50 ms
3 ms
3 ms
10
V
°C
°C
°C
mA
t
RAMP
I
Diode
Power supply ramp time
Magnitude of DC current across PCI clamp
diode when enabled
Fast POR
(7)
Instant-on
Programming/Erasure Specifications
Table 9: Programming/Erasure Specifications for MAX 10 Devices—Preliminary
This table shows the programming cycles and data retention duration of the user flash memory (UFM) and configuration flash memory (CFM) blocks.
Erase and reprogram cycles (E/P)
(8)
(Cycles/page)
Temperature (°C)
Data retention duration (Years)
10,000
10,000
85
100
20
10
DC Characteristics
I/O Pin Leakage Current
The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all V
CCIO
settings (3.3,
3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).
(6)
(7)
(8)
Each individual power supply should reach the recommended operating range within 50 ms.
Each individual power supply should reach the recommended operating range within 3 ms.
The number of E/P cycles applies to the smallest possible flash block that can be erased or programmed in each MAX 10 device. Each MAX 10 device
has multiple flash pages per device.
MAX 10 FPGA Device Datasheet
Altera Corporation