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10AX115U1F45E1SG 参数 Datasheet PDF下载

10AX115U1F45E1SG图片预览
型号: 10AX115U1F45E1SG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1150000-Cell, CMOS, PBGA1932, 45 X 45 MM, ROHS COMPLIANT, FBGA-1932]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL CORPORATION ]
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A10-DATASHEET
2015.12.31
Maximum Allowed Overshoot and Undershoot Voltage
3
Symbol
Description
Condition
Minimum
Maximum
Unit
V
CCIOREF_HPS
V
CCPLL_HPS
I
OUT
T
J
T
STG
HPS I/O pre-driver power supply
HPS PLL power supply
DC output current per pin
Operating junction temperature
Storage temperature (no bias)
–0.50
–0.50
–25
–55
–65
2.46
2.46
25
125
150
V
V
mA
°C
°C
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than
100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to
100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Table 2: Maximum Allowed Overshoot During Transitions for Arria 10 Devices—Preliminary
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O
values are applicable to the
VREFP_ADC
and
VREFN_ADC
I/O pins.
Symbol
Description
Condition (V)
LVDS I/O
(2)
3 V I/O
Overshoot Duration as % at T
J
= 100°C
Unit
2.50
2.55
Vi (AC)
AC input voltage
2.60
2.65
2.70
> 2.70
3.80
3.85
3.90
3.95
4.00
> 4.00
100
42
18
9
4
No overshoot allowed
%
%
%
%
%
%
(2)
The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
Altera Corporation
Arria 10 Device Datasheet