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10AX057H4F34I3LG 参数 Datasheet PDF下载

10AX057H4F34I3LG图片预览
型号: 10AX057H4F34I3LG
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 570000-Cell, CMOS, PBGA1152, 35 X 35 MM, ROHS COMPLIANT, FBGA-1152]
分类和应用: 可编程逻辑
文件页数/大小: 110 页 / 1391 K
品牌: INTEL [ INTEL ]
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A10-DATASHEET  
2015.12.31  
51  
DPA Lock Time Specifications  
Table 47: DPA Lock Time Specifications for Arria 10 Devices—Preliminary  
The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1  
or 1-to-0 transition.  
Standard  
Training Pattern  
Number of Data Transitions in Number of Repetitions per  
Maximum Data Transition  
(77)  
One Repetition of the  
Training Pattern  
256 Data Transitions  
SPI-4  
00000000001111111111  
00001111  
2
2
4
8
8
128  
128  
64  
640  
640  
640  
640  
640  
Parallel Rapid I/O  
Miscellaneous  
10010000  
10101010  
32  
01010101  
32  
(77)  
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.  
Arria 10 Device Datasheet  
Send Feedback  
Altera Corporation  
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