A10-DATASHEET
2015.12.31
39
I/O PLL Specifications
Symbol
Parameter
Condition
–1 speed grade
–2 speed grade
–3 speed grade
—
Min
—
Typ
—
Max
800
720
650
55
Unit
MHz
MHz
MHz
%
Output frequency for external clock
output
fOUT_EXT
—
—
—
—
tOUTDUTY
tFCOMP
fDYCONFIGCLK
tLOCK
Duty cycle for dedicated external clock
output (when set to 50%)
45
50
External feedback clock compensation
time
—
—
—
—
—
—
—
—
—
10
100
1
ns
MHz
ms
Dynamic configuration clock for
mgmt_clkand scanclk
Time required to lock from end-of-
device configuration or deassertion of
areset
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
10
—
—
50
—
ps
ns
Minimum pulse width on the areset
signal
FREF ≥ 100 MHz
FREF < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
—
—
—
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
UI (p-p)
ps (p-p)
(57)(58)
tINCCJ
Input clock cycle-to-cycle jitter
ps (p-p)
tOUTPJ_DC
Period jitter for dedicated clock output
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock
output
tOUTCCJ_DC
mUI (p-p)
(57)
(58)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter
< 120 ps.
FREF is fIN/N, specification applies when N = 1.
Arria 10 Device Datasheet
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